
module AReg(iClk, iReset, iAReg, oAReg);
	input [31:0] iAReg;
	input iReset, iClk;
	output [31:0] oAReg;
	reg [31:0] oAReg;

	always @ (posedge iReset or posedge iClk)
	begin
		if(iReset)
			oAReg <= 32'b0;
		else
			oAReg <= iAReg;
	end
	
endmodule